library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity pipeir is
	generic
	(
		DATA_WIDTH	: natural  :=	32
	);

	port
	(
		-- Input ports
		pc4 : in std_logic_vector(DATA_WIDTH-1 downto 0);
		ins : in std_logic_vector(DATA_WIDTH-1 downto 0);
		wir : in std_logic;
		clk : in std_logic;
		clrn : in std_logic;
		cen : in std_logic;
		irq : in std_logic;
		
		-- Output ports
		irqmask : out std_logic;
		pcf : out std_logic_vector(DATA_WIDTH-1 downto 0);
		inst : out std_logic_vector(DATA_WIDTH-1 downto 0)
	);
end pipeir;

architecture rtl_pipeir of pipeir is
component lpm_dffe32
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		enable		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
	);
end component;
component lpm_dffe1
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC ;
		enable		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC 
	);
end component;

signal aclr : std_logic;

begin
	aclr <= not clrn;
	pc4topcf: lpm_dffe32 port map(
		aclr => aclr,
		clock => clk,
		data => pc4,
		enable => wir and cen,
		q => pcf
	);
	
	ins2inst: lpm_dffe32 port map(
		aclr => aclr,
		clock => clk,
		data => ins,
		enable => wir and cen,
		q => inst
	);
	intmask: lpm_dffe1 port map(
		aclr => aclr,
		clock => clk,
		data => irq,
		enable => wir and cen,
		q => irqmask
	);

end rtl_pipeir;

